The invention relates to a demodulator for a frequency modulated signal, and particularly for a SECAM chrominance signal. The invention is used, for example, in applications for the manufacture of televisions or video signal receivers.
According to the SECAM standard, chrominance information in a video signal is transmitted by frequency modulation of chrominance sub-carriers. The video signal comprises a sequence of lines forming a picture. These lines include two successive lines that carry information corresponding to the red component and then corresponding to the blue component respectively, in a three-color image. The sub-carriers on which the information for the red and the blue is coded are centered on separate frequencies that are FOR=4.406 MHZ for the red, and FOB=4.250 MHZ for the blue.
Chrominance signal demodulators are used to extract information related to the red and blue components from the signal, and more precisely from frequency modulated sub-carriers. FIG. 1 shows the operating principle for a SECAM chrominance signal demodulator, in a diagrammatic and simplified manner.
The demodulator in FIG. 1 can be used to demodulate lines containing information related to the red or blue components. The demodulator consists mainly of an oscillator 10 with controlled frequency and a phase comparator 20. For the purposes of this invention, a phase comparator means a device that has two signal inputs and is capable of outputting a current or a voltage proportional to a phase difference between the two input signals.
The oscillator 10 is a voltage controlled oscillator (VCO) comprising two inputs 12, 14 called the loop input and the adjustment input respectively, and an output 16 that outputs a signal at a frequency that depends on the voltages applied at the loop and adjustment inputs. The input to the loop 12 of oscillator 10 is connected to an output 26 of the phase comparator 20, while the output 16 from oscillator 10 is connected to a first input 22 of the phase comparator. A second input 24 of the phase comparator is connected to a two-way switch 28 that selectively connects the second input either to a chrominance channel 30 that transmits the chrominance signal, or to a quartz external reference oscillator 32 that outputs a signal at a reference frequency.
The phase comparator associated with the oscillator forms a PLL (Phase Locked Loop) demodulator. When the two-way switch 28 connects the second input 24 of the phase comparator to the chrominance channel 30, the demodulator outputs a voltage V proportional to the frequency of the chrominance signal F. The voltage V is used as information representative of the color component (blue or red) corresponding to the signal present on channel 30.
The voltage V is such that V=kFU where k is a proportionality coefficient and U is a voltage applied to the adjustment input 14 of the oscillator.
The frequency of the output signal from oscillator 10 must be determined very precisely and must remain stable to control the precision of the demodulator output voltage V so that the equipment including the demodulator is disposed will be capable of high fidelity reproduction of the colors. Consequently, the oscillator 10 must be frequently matched to a reference frequency denoted Fref, supplied by the external oscillator 32.
Oscillator 10 is matched by connecting the second input 24 of the phase comparator to the external reference oscillator 32. During the oscillator matching phase, an on-off switch 40 in an adjustment circuit 42 is closed. The matching phase may then be started, for example, by information that cancels out the video signal frame used to control the two-way switch 28 and the on-off switch 40. This circuit comprises a transconductor 44, one input of which is connected to the input of oscillator loop 12, and the other input is connected to a reference voltage source 46 outputting a voltage Vref.
When the voltage at the input to the oscillator loop 10 is not equal to the reference voltage Vref, the transconductor outputs a current (positive or negative) that charges or discharges a memory capacitor 48. Thus, the voltage U of the memory capacitor 48 applied to the oscillator adjustment input 14 is modified to adjust the oscillator output voltage to a value such that the oscillator loop input voltage becomes equal to Vref.
During a demodulation phase, the on-off switch 40 is open and the adjusted voltage U is maintained at the terminals of capacitor 48.
Thus Vref=kFrefU
let   U  =            V      ref              kF      ref      
therefore:   V  =      kFU    =                  kF        ⁢                  xe2x80x83                ⁢                              V            ref                                kF            ref                              =                                                  V              ref                                      F              ref                                ⁢                      xe2x80x83                    ⁢          F                =                  H          ⁢                      xe2x80x83                    ⁢          F                    
where H is the demodulation gain that is very precisely known as the ratio of the reference voltage to the reference frequency.
The voltage U must be kept as stable as possible between two oscillator matching phases, to prevent any deterioration in the color reproduction. Even a minor modification to the adjustment voltage U causes a large modification to the oscillation frequency of oscillator 10. This modification is particularly large if the gain on the adjustment loop is large. Thus, a leakage current from the memory capacitor 48 could disturb operation of the oscillator.
In order to reduce the influence of leakage currents and to make the oscillator stable between two matching phases, the capacitance of the memory capacitor 48 is chosen to be high. For example, the capacitance of the capacitor is chosen to be between 10 and 100 nF. These capacitance values form an obstacle, n or at least a handicap, for integrating the capacitor with the other demodulator components in the form of an integrated circuit. Thus capacitor 48 is usually not integrated on the chip comprising the video signal decoder, but it is in the form of a separate component.
The object of this invention is to provide a demodulator for frequency modulated signals, and particularly for SECAM chrominance signals, without the disadvantages mentioned above.
One object is to provide such a demodulator with a low capacitance memory capacitor, particularly suitable for production in the form of an integrated circuit.
Another object is to provide such a demodulator with an oscillator with a particularly stable frequency, and which is not very sensitive to leakage currents from the memory capacitor.
To achieve these objects, the demodulating device for a frequency modulated signal comprises an oscillator with controlled frequency, forming a demodulation loop with a phase comparator, and an adjuster for adjusting the oscillator frequency as a function of a charge voltage of a memory capacitor connected to an oscillator adjustment input.
The adjuster according to the invention comprises a fine adjustment channel to output a first adjustment value at the oscillator adjustment input, that depends on the voltage of the memory capacitor, and a coarse adjustment channel. The coarse adjustment channel outputs a second adjustment value added to the first adjustment value at the oscillator input. The second adjustment value is increased when the capacitor voltage exceeds a high limitation voltage or first threshold and is reduced when the capacitor voltage is below a low limitation voltage or second threshold.
The charging voltage of the capacitor may be fixed by appropriate means during an oscillator matching phase, for example as described previously with reference to FIG. 1.
The coarse adjustment channel may be designed to output an adjustment value that preferably corresponds to a majority fraction of the total adjustment value applied to the oscillator input. This adjustment value is not affected by any parasitic variation and is maintained independent of the variation of the state of charge of the capacitor between two oscillator matching phases.
The fine adjustment channel still contributes to variations in the charge of the memory capacitor. However, since this channel only supplies part (preferably a minority part) of the adjustment value, the total adjustment value supplied to the oscillator remains fairly insensitive to leakage currents that could affect the memory capacitor. Therefore, this capacitor may be made with a capacitance value less than what was usually used in prior art. Furthermore, the capacitor can then be made with other components of the device in the form of an integrated circuit.
The oscillator in the device according to the invention may be a voltage controlled oscillator (VCO), or a current controlled oscillator (CCO). In the first case, voltages are applied to the oscillator inputs, and in the second case, currents are applied to the oscillator inputs. Thus the term xe2x80x9cadjustment valuexe2x80x9d may be understood as an adjustment voltage or as an adjustment current, depending on the oscillator type used.
In one particular embodiment of the fine adjustment channel, the fine adjustment may comprise an amplifier with an input connected to the memory capacitor and an output connected to the oscillator adjustment input, outputting the first adjustment value proportional to the capacitor charge voltage. For example, the amplifier may be a transconductor amplifier to convert the capacitor charge voltage into an adjustment current for a CCO type oscillator.
According to one variant, the capacitor may be connected directly through a voltage adder to the input of a VCO type oscillator. In this case the voltage adder can add adjustment voltages from the coarse and fine adjustment channels.
The coarse adjustment channel may comprise a digital-analog converter connected to the oscillator adjustment input to output an adjustment value corresponding to a coded digital value, and a modifier for modifying the digital value when the voltage of the memory capacitor is outside the voltage range between the high and low limitation voltages. Thus, low drops in the voltage of the memory capacitor due to leakage currents, which are insufficient to make the charge voltage drop below the low limitation voltage, do not cause any modifications to the coded digital value.
The digital value (for example, stored in a memory register) may be kept unchanged between two oscillator matching phases, in other words during demodulation phases. The modifier is usually only activated during an oscillator matching phase, when the capacitor charge voltage is no longer within the range of voltages between the high and low limitation voltages.
In one specific embodiment, the modifier may include a first comparator to compare the memory capacitor charge voltage with a low limitation voltage, and connected to the converter to reduce the coded digital value when the charge voltage is less than the low limitation value. A second comparator is provided to compare the capacitor charge voltage with a high limitation voltage and is connected to the converter to increase the coded digital value when the charge voltage exceeds the high limitation voltage.
Preferably, the increase and reduction in the memorized digital value occur in response to increasing and reducing pulses. The comparator output is a continuous output (high or low) rather than a pulse output, reflecting the value of the charge voltage compared with the corresponding limitation voltage. Thus, the first and second comparators may be coupled to a clock pulse generator to output pulses to the digital-analog converter to reduce or increase the digital value at each clock pulse until the charge voltage is between the high and low limitation voltages.
The digital value may be coded on a number N of bits and may be modified by a quantity corresponding to a lower order bit for each pulse. The digital-analog converter is then designed so that a modification of the digital value by a quantity corresponding to a lower order bit will result in a modification to the second adjustment value less than the maximum modification of the first adjustment value output by the fine adjustment channel. This is done in response to a variation in the capacitor charge voltage equal to the difference between the high limitation voltage and the low limitation voltage. Modifications to the second adjustment value output in response to a modification to the digital value exceeding a lower order bit are preferably larger than modifications to the first adjustment value of the fine adjustment channel.
According to one particular aspect, the device according to the invention may comprise a transconductor amplifier with input terminals connected to the terminals of a resistor through which an electric current passes that varies linearly with the current applied to the oscillator loop input, and with a current output terminal that can be connected to the memory capacitor during an oscillator matching phase. This type of manufacturing is particularly suitable for a CCO type oscillator. The oscillator loop input is connected to the phase comparator output to form a demodulation loop. The oscillator loop input also forms the demodulator output.
An on-off switch may be actuated to connect the transconductor amplifier output to the memory capacitor during oscillator matching phases. The phase comparator input is connected to a reference frequency generator during these matching phases.
According to one variant corresponding to a system including a VCO type oscillator, the device may also comprise a transconductor amplifier with a first input terminal connected to the oscillator loop input, and a second input terminal connected to a reference voltage source. A current output terminal is connected to the memory capacitor through an on-off switch.
The invention also relates to the use of the device described above as a SECAM chrominance signals demodulator.